10/3 硬體描述語言

module top;
system_clock #100 clock1(A);
system_clock #200 clock1(B);
system_clock #400 clock1(SEL);
mux  mm1(OUT,A,B,SEL);
endmodule

module mux(OUT,A,B,SEL);
output OUT;
input A,B,SEL;

not I5(sel_n, SEL);

and I6(sel_a,A,SEL);
and I7(sel_b,sel_n,B);

or I4(OUT,sel_a,sel_b);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule