11/7 硬體描述語言 一位元加法器

module top;
system_clock #100clock1(A);
system_clock #200clock1(B);
system_clock #400clock1(Cin);
adder  dogking(Cout, Sum, A, B, Cin);
endmodule

module adder (Cout, Sum, A, B, Cin);
output Cout, Sum;
input A, B, Cin;
and dog1 (ab_n, A, B);
xor dog2 (ab1_n, A, B);
and dog3 (xo, ab1_n, Cin);
xor dog4 (Sum, ab1_n, Cin);
or  dog5 (Cout, ab_n, xo);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule