f9903216
2011年11月21日 星期一
11/21 硬體描述語言 8bits Adder
endmodule
module adder (Cout, Sum, A, B, Cin);
output Cout, Sum;
input A, B, Cin;
and dog1 (ab_n, A, B);
xor dog2 (ab1_n, A, B);
and dog3 (xo, ab1_n, Cin);
xor dog4 (Sum, ab1_n, Cin);
or dog5 (Cout, ab_n, xo);
endmodule
module adder8(Cout, Sum, A, B, Cin);
output Cout;
output [7:0]Sum;
input [7:0]A, B ;
input Cin;
adder4 dog1(Cat, Sum[3:0], A[3:0], B[3:0] ,Cin);
adder4 dog2(Cout, Sum[7:4], A[7:4], B[7:4], Cat);
endmodule
module adder4(Cout, Sum, A, B, Cin);
output Cout;
output [3:0]Sum;
input [3:0]A, B ;
input Cin;
adder2 dog1(Cat, Sum[1:0], A[1:0], B[1:0] ,Cin);
adder2 dog2(Cout, Sum[3:2], A[3:2], B[3:2], Cat);
endmodule
module adder2(Cout, Sum, A, B, Cin);
output Cout;
output [1:0]Sum;
input [1:0]A, B ;
input Cin;
adder dog1(Cat, Sum[0], A[0], B[0] ,Cin);
adder dog2(Cout, Sum[1], A[1], B[1], Cat);
endmodule
2011年11月7日 星期一
11/7 硬體描述語言 一位元加法器
module top;
system_clock #100clock1(A);
system_clock #200clock1(B);
system_clock #400clock1(Cin);
adder dogking(Cout, Sum, A, B, Cin);
endmodule
module adder (Cout, Sum, A, B, Cin);
output Cout, Sum;
input A, B, Cin;
and dog1 (ab_n, A, B);
xor dog2 (ab1_n, A, B);
and dog3 (xo, ab1_n, Cin);
xor dog4 (Sum, ab1_n, Cin);
or dog5 (Cout, ab_n, xo);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule
system_clock #100clock1(A);
system_clock #200clock1(B);
system_clock #400clock1(Cin);
adder dogking(Cout, Sum, A, B, Cin);
endmodule
module adder (Cout, Sum, A, B, Cin);
output Cout, Sum;
input A, B, Cin;
and dog1 (ab_n, A, B);
xor dog2 (ab1_n, A, B);
and dog3 (xo, ab1_n, Cin);
xor dog4 (Sum, ab1_n, Cin);
or dog5 (Cout, ab_n, xo);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule
2011年10月17日 星期一
10/17 Verilog 課堂操作
module hello1;
initial $display("Hello Verilog");
endmodule
initial $display("Hello Verilog");
endmodule
module hello1;
initial $display ("Hello\n Verilog");
endmodule
initial $display ("Hello\n Verilog");
endmodule
與C程式 \n 換行 具有相同的效果。
2011年10月3日 星期一
10/3 硬體描述語言
module top;
system_clock #100 clock1(A);
system_clock #200 clock1(B);
system_clock #400 clock1(SEL);
mux mm1(OUT,A,B,SEL);
endmodule
module mux(OUT,A,B,SEL);
output OUT;
input A,B,SEL;
output OUT;
input A,B,SEL;
not I5(sel_n, SEL);
and I6(sel_a,A,SEL);
and I7(sel_b,sel_n,B);
and I7(sel_b,sel_n,B);
or I4(OUT,sel_a,sel_b);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule
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